Role of a CPU in Program Execution

Fundamental Concepts of Program Execution

• A typical computing task consists of a series of steps specified by a sequence of machine instructions that constitute a program
• To execute a program, the processor fetches one instruction at a time and performs the execution specified in that machine instruction
• Instructions are fetched from successive memory locations until a branch or a jump instruction is encountered

Organization of a Digital Computer

• In addition to ALU, CPU consists of a Control Unit (CU) and a number of registers for storage and execution of machine instructions
• The coordination among various units of a computer such as memory, ALU and input and output units are coordinated by the control circuitry (also called Control Unit)

Here is a Presentation on the Role of a CPU.

Program Counter (PC):

• The processor keeps track of the address of the memory location containing the next machine instruction to be fetched using a special register called Program Counter (PC)
• After fetching an instruction using PC, the contents of the PC will be updated to point to the next machine instruction available in the sequence
• A branch instruction may load a different value (memory address) into the PC.

Instruction Register (IR):

• Another key register available in the processor is the Instruction Register (IR)
• IR holds the instruction that is currently being executed in the CPU
• The instruction available in IR is decoded by the CPU and the necessary signals are generated by the CU to control the various processing elements involved in executing the machine instruction being decoded 
• Suppose that an instruction occupies 4 bytes in memory, it has to go through the following three-step process in the CPU for its execution:  

Step-1: Fetch the contents of the memory location pointed to by the PC. The contents of this location are interpreted as an instruction to be executed. Hence, they are loaded into the IR. Symbolically, this an be written as 

                IR ← [[PC]] 

Step-2: Assuming that the memory is byte addressable, increment the contents of the PC by 4, that is,

                                    PC ← [PC] + 4

Step-3: Carry out the actions specified by the instruction in the IR.

• In cases the instruction being executed occupies more than one word (4 bytes), steps 1 and 2 must be repeated as many times as necessary to fetch the complete instruction. 
• The first two steps are usually referred to as the fetch phase: step 3 constitutes the execution phase.

Internal Organization of the Processor:

• A simple organization of a Processor is given below:

• In this simple organization of a processor, the Arithmetic and Logic Unit (ALU) and all the registers are interconnected via single common bus. 
• The bus is internal to the processor (called CPU Bus) and should not be confused with the external bus that connects the processor to the memory and I/O devices. 
• The data and address lines of the external memory bus are (shown in the above figure) connected to the internal processor bus via the memory data register, MDR, and the Memory Address Register (MAR), respectively.

MDR, MAR and IR:

• Register MDR has two inputs and two outputs. Data may be loaded into MDR either from the memory bus or from the internal processor bus for input. 
• The data stored in MDR may be placed on either bus for output. 
• The input of MAR is connected to the internal bus, and its output is connected to the external bus. 
• The output of the Instruction Register (IR) is connected to the instruction decoder and control logic block, which is responsible for issuing the signals that control the operation of all the units inside the processor and the external memory.

Other Registers Inside the CPU:

• The number and use of the processor registers R0 through R(n-1) vary considerably from one processor to another. They are provided for general-purpose use by the programmer. 
• Some may be dedicated as special-purpose registers, such as index registers or stack pointers.  Three registers, X, Y, and TEMP are shown in the above figure.
• Special-purpose registers are not meant for the programmer, that is, the programmer need not be concerned with them because they are never referenced explicitly by any instruction.
• They are used by the processor for temporary storage during execution of some instruction.
• These registers are never used for storing data generated by one instruction to be used by another instruction at a later stage.

ALU and Control Unit (CU):

• As instruction execution progresses, data are transferred from one register to another, often passing through the ALU to perform some arithmetic or logic operation. 
• The instruction decoder and control logic unit is responsible for implementing the actions specified by the instruction loaded in the IR register. 
• The decoder generates the control signals needed to select the registers involved and direct the transfer of data.
• The registers, the ALU, and the interconnection bus are collectively referred to as the datapath.

Performing Arithmetic or Logical Operation in ALU:

• The ALU is a combinational circuit that has no internal storage. It performs arithmetic and logic operations on the two operands applied to its A and B inputs. 
• As shown in the figure above for internal organization of a processor, one of the operands is the output of the register X and the other operand is obtained directly from the bus.
• The result produced by the ALU is stored temporarily in register Y. 
•  Therefore, a sequence of operations need to be performed to add the contents of register R1 to those of register R2 and store the result in register R3:

1.  R1out , Xin 
2.  R2out, Xout, Yin 
3.  Yout, R3in

• The signals whose names are given in any step are activated for the duration of the clock cycle corresponding to that step. All other signals are inactive. 
• Hence, in step 1, the output of register R1 and the input of register X are enabled, causing the contents of R1 to be transferred over the bus to X.
• In step 2, the output of register R2, and the output of register X are enabled, causing the content of R1 and R2 to be added by the ALU.

Storing the Result in R3:

• The function performed by the ALU depends on the signals applied to its control lines. 
• In this case, the Add line is set to 1, causing the output of ALU to be the sum of the two numbers given as input A and B. 
• The result of this addition is loaded into register Y because its input control signal is activated. 
• In step 3, the content of register Y is transferred to the destination register, R3. 
• This last transfer can' t be carried out during step 2, because only one register output can be connected to the bus during any clock cycle.