Bus and Memory Transfers

•  A typical digital computer has many registers, and paths must be provided to transfer information from one register to another. 
• The number of wires will be excessive if separate lines are used between each register and all other registers i n the system. 
• A more efficient scheme for transferring information between registers in a multiple-register configuration is a common bus system. 
• A bus structure consists of a set of common lines, one for each bit of a register, through which binary information is transferred one at a time. 
• Control signals determine which register is selected by the bus during each particular register transfer.

Use of Multiplexer in Bus Transfer:

• One way of constructing a common bus system is with multiplexers. 
• The multiplexers select the source register whose binary information is then placed on the bus. 
• The construction of a bus system for four registers is shown in Fig. 4-3. 

• Each register has four bits, numbered 0 through 3. 
• The bus consists of four 4 x 1 multiplexers each having four data inputs, 0 through 3, and two selection inputs, S1 and S0
• The bits in the same significant position from each register are connected to the data inputs of one multiplexer to form one line of the bus. 
• Thus MUX 0 multiplexes the four 0 bits of the registers, MUX 1 multiplexes the four 1 bits of the registers, and similarly for the other two bits. 

Bus Selection for 4-bit Registers:

• The two selection lines S1 and S0 are connected to the selection inputs of all four multiplexers. 
• The selection lines choose the four bits of one register and transfer them into the four-line common bus. 
• When S1S0 = 00, the 0 data inputs of all four multiplexers are selected and applied to the outputs that form the bus. This causes the bus lines to receive the content of register A since the outputs of this register are connected to the 0 data inputs of the multiplexers. 
• Similarly, register B is selected if S1S0 = 01, and so on. 

• Table 4-2 shows the register that is selected by the bus for each of the four possible binary value of the selection lines.
• In general, a bus system will multiplex k registers of n bits each to produce an n-line common bus. 
• The number of multiplexers needed to construct the bus is equal to n, the number of bits in each register. 
• The size of each multiplexer must be k x 1 since it multiplexes k data lines.

8-bit Multiplexer for Data Transfer:

• For example, a common bus for eight registers of 16 bits each requires 16 multiplexers, one for each line in the bus. 
• Each multiplexer must have eight data input lines and three selection lines to multiplex one significant bit in the eight registers.

Symbolic Representation of Data Transfer in a Bus:

• The transfer of information from a bus into one of many destination registers can be accomplished by connecting the bus lines to the inputs of all destination registers and activating the load control of the particular destination register selected. 
• The symbolic statement for a bus transfer may mention the bus or its presence may be implied in the statement. 
• When the bus is explicitly mentioned in the statement, the register transfer is represented as follows:
  

BUS ← C,

R 1 ← BUS

• This symbolic representation implies that the content of register C is placed on the bus, and the content of the bus is loaded into register R 1 by activating its load control input. 
• If the bus is known to exist (implicitly) in the system, it may be convenient just to show the direct transfer.
  

R1 ← C

Three-State Bus Buffers:

• A bus system can be constructed with three-state gates instead of multiplexers. 
• A three-state gate is a digital circuit that exhibits three states.
• Two of the states are signals equivalent to logic 1 and 0 as in a conventional gate.  The third state is a high-impedance state.
• The high-impedance state behaves like an open circuit, which means that the output is disconnected and does not have a logic significance.
• Three-state gates may perform any conventional logic, such as AND or NAND.

Memory Transfer

• The transfer of information from a memory word to the outside environment is called a read operation.
• A memory word will be symbolized by the letter M .
• The particular memory word among the many available is selected by the memory address during the transfer.
• It is necessary to specify the address of M when writing memory transfer operations.
• This will be done by enclosing the address in square brackets following the letter M .

Memory Read:

• Consider a memory unit that receives the address from a register, called
  the address register, symbolized by AR .
• The data are transferred to another register, called the data register, symbolized by DR.
• The read operation can be stated as follows:

                Read: DR ← M [AR]

• This causes a transfer of information into DR from the memory word M selected by the address in AR.

Memory Write:

• The write operation transfers the content of a data register to a memory word M selected by the address.
• Assume that the input data are in register Rl

• R2' is the symbol for the 1's complement of R2.
• Adding 1 to the 1' s complement produces the 2' s complement.
• Adding the contents of R1 to the 2' s complement of R2 is equivalent to R1 - R2.
• The result will be stored in R3 by transferring the data from ALU to R3 via the central bus and then to the external memory using its memory address.